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Structured Low-Density Parity-Check Codes with Bandwidth Efficient ModulationIn this work, we study the performance of structured Low-Density Parity-Check (LDPC) Codes together with bandwidth efficient modulations. We consider protograph-based LDPC codes that facilitate high-speed hardware implementations and have minimum distances that grow linearly with block sizes. We cover various higher- order modulations such as 8-PSK, 16-APSK, and 16-QAM. During demodulation, a demapper transforms the received in-phase and quadrature samples into reliability information that feeds the binary LDPC decoder. We will compare various low-complexity demappers and provide simulation results for assorted coded-modulation combinations on the additive white Gaussian noise and independent Rayleigh fading channels.
Document ID
20150008336
Document Type
Conference Paper
External Source(s)
Authors
Cheng, Michael K. (Jet Propulsion Lab., California Inst. of Tech. Pasadena, CA, United States)
Divsalar, Dariush (Jet Propulsion Lab., California Inst. of Tech. Pasadena, CA, United States)
Duy, Stephanie (Jet Propulsion Lab., California Inst. of Tech. Pasadena, CA, United States)
Date Acquired
May 18, 2015
Publication Date
April 13, 2009
Subject Category
Computer Programming and Software
Meeting Information
SPIE Defense, Security and Sensing Conference(Orlando, FL)
Distribution Limits
Public
Copyright
Other
Keywords
Crew Exploration Vehicle (CEV)
Constellation