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Record 1 of 1788
FPGA Verification Accelerator (FVAX)
External Online Source: hdl:2014/45341
Author and Affiliation:
Oh, Jane(Jet Propulsion Lab., California Inst. of Tech., Pasadena, CA, United States)
Burke, Gary(Jet Propulsion Lab., California Inst. of Tech., Pasadena, CA, United States)
Abstract: Is Verification Acceleration Possible? - Increasing the visibility of the internal nodes of the FPGA results in much faster debug time - Forcing internal signals directly allows a problem condition to be setup very quickly center dot Is this all? - No, this is part of a comprehensive effort to improve the JPL FPGA design and V&V process.
Publication Date: Sep 15, 2008
Document ID:
20150014710
(Acquired Aug 03, 2015)
Subject Category: ELECTRONICS AND ELECTRICAL ENGINEERING
Document Type: Oral/Visual Presentation
Meeting Information: Military and Aerospace Programmable Logic Devices (MAPLD) Conference; 15-18 Sep. 2008; Annapolis, MD; United States
Meeting Sponsor: NASA Goddard Space Flight Center; Greenbelt, MD, United States
Financial Sponsor: Jet Propulsion Lab., California Inst. of Tech.; Pasadena, CA, United States
Description: 14p; In English
Distribution Limits: Unclassified; Publicly available; Unlimited
Rights: Copyright
NASA Terms: FIELD-PROGRAMMABLE GATE ARRAYS; VISIBILITY; CHECKOUT; PROGRAM VERIFICATION (COMPUTERS); ARCHITECTURE (COMPUTERS); SYSTEMS ANALYSIS; SIMULATION
Availability Source: Other Sources
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