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FPGA Verification Accelerator (FVAX)Is Verification Acceleration Possible? - Increasing the visibility of the internal nodes of the FPGA results in much faster debug time - Forcing internal signals directly allows a problem condition to be setup very quickly center dot Is this all? - No, this is part of a comprehensive effort to improve the JPL FPGA design and V&V process.
Document ID
20150014710
Acquisition Source
Jet Propulsion Laboratory
Document Type
Presentation
External Source(s)
Authors
Oh, Jane
(Jet Propulsion Lab., California Inst. of Tech. Pasadena, CA, United States)
Burke, Gary
(Jet Propulsion Lab., California Inst. of Tech. Pasadena, CA, United States)
Date Acquired
August 3, 2015
Publication Date
September 15, 2008
Subject Category
Electronics And Electrical Engineering
Meeting Information
Meeting: Military and Aerospace Programmable Logic Devices (MAPLD) Conference
Location: Annapolis, MD
Country: United States
Start Date: September 15, 2008
End Date: September 18, 2008
Sponsors: NASA Goddard Space Flight Center
Distribution Limits
Public
Copyright
Other

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