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Processing and Prolonged 500 C Testing of 4H-SiC JFET Integrated Circuits with Two Levels of Metal InterconnectComplex integrated circuit (IC) chips rely on more than one level of interconnect metallization for routing of electrical power and signals. This work reports the processing and testing of 4H-SiC junction field effect transistor (JFET) prototype IC's with two levels of metal interconnect capable of prolonged operation at 500 C. Packaged functional circuits including 3- and 11-stage ring oscillators, a 4-bit digital to analog converter, and a 4-bit address decoder and random access memory cell have been demonstrated at 500 C. A 3-stage oscillator functioned for over 3000 hours at 500 C in air ambient. Improved reproducibility remains to be accomplished.
Document ID
20160005308
Acquisition Source
Glenn Research Center
Document Type
Conference Paper
Authors
Spry, David J.
(NASA Glenn Research Center Cleveland, OH United States)
Neudeck, Philip G.
(NASA Glenn Research Center Cleveland, OH United States)
Chen, Liangyu
(Ohio Aerospace Inst. Brook Park, OH, United States)
Lukco, Dorothy
(Vantage Partners, LLC Brook Park, OH, United States)
Chang, Carl W.
(Vantage Partners, LLC Brook Park, OH, United States)
Beheim, Glenn M.
(NASA Glenn Research Center Cleveland, OH United States)
Krasowski, Michael J.
(NASA Glenn Research Center Cleveland, OH United States)
Prokop, Norman F.
(NASA Glenn Research Center Cleveland, OH United States)
Date Acquired
April 25, 2016
Publication Date
October 4, 2015
Subject Category
Electronics And Electrical Engineering
Report/Patent Number
GRC-E-DAA-TN26971
Meeting Information
Meeting: International Conference on Silicon Carbide and Related Materials
Location: Sicily
Country: Italy
Start Date: October 4, 2015
End Date: October 9, 2015
Sponsors: Trans Tech Publications Ltd.
Funding Number(s)
CONTRACT_GRANT: NNC13BA10B
WBS: WBS 359615.01.99.99.99.99.22
CONTRACT_GRANT: NNC12BA01B
Distribution Limits
Public
Copyright
Public Use Permitted.
Keywords
JFET
Microelectronics
Silicon Carbide
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