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NEPP Update of Independent Single Event Upset Field Programmable Gate Array TestingThis presentation provides a NASA Electronic Parts and Packaging (NEPP) Program update of independent Single Event Upset (SEU) Field Programmable Gate Array (FPGA) testing including FPGA test guidelines, Microsemi RTG4 heavy-ion results, Xilinx Kintex-UltraScale heavy-ion results, Xilinx UltraScale+ single event effect (SEE) test plans, development of a new methodology for characterizing SEU system response, and NEPP involvement with FPGA security and trust.
Document ID
20170005805
Acquisition Source
Goddard Space Flight Center
Document Type
Presentation
Authors
Berg, Melanie
(ASRC Federal Space and Defense Greenbelt, MD, United States)
Label, Kenneth
(NASA Goddard Space Flight Center Greenbelt, MD United States)
Campola, Michael
(NASA Goddard Space Flight Center Greenbelt, MD United States)
Pellish, Jonathan
(NASA Headquarters Washington, DC United States)
Date Acquired
June 28, 2017
Publication Date
June 26, 2017
Subject Category
Electronics And Electrical Engineering
Quality Assurance And Reliability
Report/Patent Number
GSFC-E-DAA-TN43723
Meeting Information
Meeting: NEPP Electronics Technology Workshop
Location: Greenbelt, MD
Country: United States
Start Date: June 26, 2017
End Date: June 29, 2017
Sponsors: NASA Goddard Space Flight Center
Funding Number(s)
CONTRACT_GRANT: NNG13CR48C
Distribution Limits
Public
Copyright
Public Use Permitted.
Keywords
Field Programmable Gate Array (FPGA); Triple Modular Redundancy; N-M Redundancy;
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