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Engineering Trade-off Considerations Regarding Design-for-Security, Design-for-Verification, and Design-for-TestThe United States government has identified that application specific integrated circuit (ASIC) and field programmable gate array (FPGA) hardware are at risk from a variety of adversary attacks. This finding affects system security and trust. Consequently, processes are being developed for system mitigation and countermeasure application. The scope of this tutorial pertains to potential vulnerabilities and countermeasures within the ASIC/FPGA design cycle. The presentation demonstrates how design practices can affect the risk for the adversary to: change circuitry, steal intellectual property, and listen to data operations. An important portion of the design cycle is assuring the design is working as specified or as expected. This is accomplished by exhaustive testing of the target design. Alternatively, it has been shown that well established schemes for test coverage enhancement (design-for-verification (DFV) and design-for-test (DFT)) can create conduits for adversary accessibility. As a result, it is essential to perform a trade between robust test coverage versus reliable design implementation. The goal of this tutorial is to explain the evolution of design practices; review adversary accessibility points due to DFV and DFT circuitry insertion (back door circuitry); and to describe common engineering trade-off considerations for test versus adversary threats.
Document ID
20180002848
Acquisition Source
Goddard Space Flight Center
Document Type
Presentation
External Source(s)
Authors
Berg, Melanie
(Arctic Slope Regional Corp. (ASRC) Federal Greenbelt, MD, United States)
Label, Kenneth
(NASA Goddard Space Flight Center Greenbelt, MD, United States)
Date Acquired
May 16, 2018
Publication Date
May 3, 2018
Subject Category
Electronics And Electrical Engineering
Report/Patent Number
GSFC-E-DAA-TN55897
GSFC-E-DAA-TN65961
Meeting Information
Meeting: HOST 2018 IEEE International Symposium on Hardware Oriented Security and Trust
Location: McLean, VA
Country: United States
Start Date: April 30, 2018
End Date: May 4, 2018
Sponsors: Institute of Electrical and Electronics Engineers
Funding Number(s)
CONTRACT_GRANT: NNG13CR48C
Distribution Limits
Public
Copyright
Portions of document may include copyright protected material.
Technical Review
Single Expert
Keywords
Design for reliability (DFR)
Design for security (DFS)
Design for test (DFT)
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