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Technical Primer on Design and SPICE Modeling of Circuits for NASA Glenn SiC JFET IC Version 12 Prototype Wafer Run - Part 2: SiC Resistor Behavior and SPICE ModelingThis presentation illustratively communicates how to SPICE model integrated silicon carbide (SiC) SiC resistors for designing circuits for NASA GRC's upcoming prototype fabrication of SiC JFET IC Version 12.
Document ID
20190026452
Acquisition Source
Glenn Research Center
Document Type
Presentation
Authors
Neudeck, Philip G. (NASA Glenn Research Center Cleveland, OH, United States)
Date Acquired
June 18, 2019
Publication Date
May 1, 2019
Subject Category
Electronics And Electrical Engineering
Report/Patent Number
GRC-E-DAA-TN68636
Report Number: GRC-E-DAA-TN68636
Meeting Information
Meeting: HOTTech Microelectronics and Sensors Subgroup Monthly Meeting
Location: Online
Start Date: May 24, 2019
Sponsors: NASA Glenn Research Center
Funding Number(s)
WBS: 161682.04.03.01.18
Distribution Limits
Public
Copyright
Work of the US Gov. Public Use Permitted.

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