NASA Logo

NTRS

NTRS - NASA Technical Reports Server

Back to Results
SEU hardening of CMOS memory circuitThis paper reports a design technique to harden CMOS memory circuits against Single Event Upset (SEU) in the space environment. A RAM cell and Flip Flop design are presented to demonstrate the method. The Flip Flop was used in the control circuitry for a Reed Solomon encoder designed for the Space Station.
Document ID
19940004346
Acquisition Source
Legacy CDMS
Document Type
Conference Paper
Authors
Whitaker, S.
(Idaho Univ. Moscow, ID, United States)
Canaris, J.
(Idaho Univ. Moscow, ID, United States)
Liu, K.
(Idaho Univ. Moscow, ID, United States)
Date Acquired
August 16, 2013
Publication Date
November 6, 1990
Publication Information
Publication: The 2nd 1990 NASA SERC Symposium on VLSI Design
Subject Category
Electronics And Electrical Engineering
Accession Number
94N71101
Distribution Limits
Public
Copyright
Public Use Permitted.
No Preview Available