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high-performance spaceflight computing (hpsc) project overviewThe High Performance Spaceflight Computing (HPSC) multi-core processor Chiplet will provide a nearly two orders-of-magnitude improvement above the current state of the art for spaceflight processors, while also providing an unprecedented flexibility to tailor performance, power consumption, and fault tolerance to meet widely varying mission needs. These advancements will provide game changing improvements in computing performance, power efficiency, and flexibility, which will significantly improve the onboard processing capabilities of future NASA and Air Force space missions. HPSC is funded by NASA's Space Technology Mission Directorate (STMD), Science Mission Directorate (SMD), and the United States Air Force. The HPSC project is managed by Jet Propulsion Laboratory, and the HPSC contract is managed by NASA Goddard Space Flight Center (GSFC). Within the HPSC project, Boeing is under contract to NASA to develop prototype Chiplets, system software, and evaluation boards. As another development within the project, NASA Goddard Space Flight Center (GSFC) and the Jet Propulsion Laboratory (JPL) are developing middleware that will simplify application development for HPSC-based onboard processors.
Document ID
Document Type
Powell, Wesley A.
(NASA Goddard Space Flight Center Greenbelt, MD, United States)
Date Acquired
November 13, 2018
Publication Date
November 5, 2018
Subject Category
Computer Systems
Astronautics (General)
Report/Patent Number
Meeting Information
Radiation Hardened Electronics Technology Conference (RHET) 2018(Phoenix, AZ)
Distribution Limits
Portions of document may include copyright protected material.
multi-core processor
spaceflight computing
onboard processing

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