Yearlong 500 °C Operational Demonstration of Up-Scaled 4H-SiC JFET Integrated Circuits

This work describes recent progress in the design, processing, upscaling, and testing of 500°C durable two-level interconnect 4H-SiC JFET IC technology undergoing development at NASA Glenn Research Center. For the first time, stable electrical operation of semiconductor ICs for 1 year (8760 hours) at 500°C in air atmosphere is reported. These groundbreaking durability results were attained on two-level interconnect JFET demonstration ICs with 175 or more transistors on each chip. This corresponds to a more than 7-fold increase in 500°C-durable circuit complexity from the 24 transistor ring oscillator ICs reported at HiTEC 2016.