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Improved circuit minimizes generation time of pseudonoise check bitsComputer switching network consists of parallel and series combinations of mod 2 adders using the minimum number of gating levels. This network minimizes the propagation time in which a sequence of pseudonoise check bits are generated.
Document ID
19650000273
Acquisition Source
Legacy CDMS
Document Type
Other - NASA Tech Brief
Authors
Anderson, T. O.
Lusbaugh, W. A.
Date Acquired
August 2, 2013
Publication Date
September 1, 1965
Subject Category
Electronic Components And Circuits
Report/Patent Number
JPL-698
Report Number: JPL-698
Accession Number
65B10275
Funding Number(s)
CONTRACT_GRANT: NAS7-100
Distribution Limits
Public
Copyright
Work of the US Gov. Public Use Permitted.

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