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A technique to eliminate false lock in PCM demodulationOne loop provides error signal which adjusts voltage controlled oscillator. Second loop multiplies input signal with generated in-phase signal. Both signals are integrated over bit period. First loop detects null which indicates lockup, and second loop emphasizes impact signal information.
Document ID
19730000106
Acquisition Source
Legacy CDMS
Document Type
Other - NASA Tech Brief
Authors
Kobayashi, H. S.
Date Acquired
August 7, 2013
Publication Date
May 1, 1973
Subject Category
Electronic Systems
Report/Patent Number
MSC-12494
Report Number: MSC-12494
Accession Number
73B10106
Distribution Limits
Public
Copyright
Work of the US Gov. Public Use Permitted.
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