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A method for polycrystalline silicon delineation applicable to a double-diffused MOS transistorMethod is simple and eliminates requirement for unreliable special etchants. Structure is graded in resistivity to prevent punch-through and has very narrow channel length to increase frequency response. Contacts are on top to permit planar integrated circuit structure. Polycrystalline shield will prevent creation of inversion layer in isolated region.
Document ID
19740000234
Acquisition Source
Legacy CDMS
Document Type
Other - NASA Tech Brief
Authors
Halsor, J. L. (Westinghouse Elec. Corp.)
Lin, H. C. (Westinghouse Elec. Corp.)
Date Acquired
August 7, 2013
Publication Date
December 1, 1974
Subject Category
Electronic Components And Circuits
Report/Patent Number
LAR-11536
LAR-11598
Report Number: LAR-11536
Report Number: LAR-11598
Accession Number
74B10234
Distribution Limits
Public
Copyright
Work of the US Gov. Public Use Permitted.

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