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Binary phase lock loops for simplified OMEGA receiversA sampled binary phase lock loop is proposed for periodically correcting OMEGA receiver internal clocks. The circuit is particularly simple to implement and provides a means of generating long range 3.4 KHz difference frequency lanes from simultaneous pair measurements.
Document ID
19760005956
Acquisition Source
Legacy CDMS
Document Type
Contractor Report (CR)
Authors
Burhans, R. W. (Ohio Univ. Athens, OH, United States)
Date Acquired
September 3, 2013
Publication Date
March 1, 1974
Subject Category
Aircraft Communications And Navigation
Report/Patent Number
NASA-CR-145811
TM-5
Report Number: NASA-CR-145811
Report Number: TM-5
Accession Number
76N13044
Funding Number(s)
CONTRACT_GRANT: NGR-36-009-017
Distribution Limits
Public
Copyright
Work of the US Gov. Public Use Permitted.

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