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RS-232 communications analyzer module for HP-1602A logic analyzerThe design and construction of a simple ASCII analyzer is described. It was built to interface directly to a Hewlett-Packard 1602A logic state analyzer but the circuitry could easily be configured to operate with any logic analyzer. The design of the ASCII analyzer allows the use of all the trace and delay functions for the HF-1602A. The ASCII analyzer circuit utilizes two universal Asynchronous Receiver/Transmitters (UAR/Ts) to simultaneously examine both the transmit and receive serial data lines. Baud rates from 300 to 9600 bits per second are selectable with the externally mounted DIP switch. The unit requires no external power supply connection and all of the integrated circuits are CMOS for low power consumption.
Document ID
19830011214
Acquisition Source
Legacy CDMS
Document Type
Contractor Report (CR)
Authors
Yost, S. R.
(Ohio Univ. Athens, OH, United States)
Date Acquired
September 4, 2013
Publication Date
February 1, 1983
Subject Category
Computer Operations And Hardware
Report/Patent Number
NAS 1.26:169962
NASA-CR-169962
TM(NASA)-86
Report Number: NAS 1.26:169962
Report Number: NASA-CR-169962
Report Number: TM(NASA)-86
Accession Number
83N19485
Funding Number(s)
CONTRACT_GRANT: NGR-36-009-017
Distribution Limits
Public
Copyright
Work of the US Gov. Public Use Permitted.
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