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High density circuit technology, part 2A multilevel metal interconnection system for very large scale integration (VLSI) systems utilizing polyimides as the interlayer dielectric material is described. A complete characterization of polyimide materials is given as well as experimental methods accomplished using a double level metal test pattern. A low temperature, double exposure polyimide patterning procedure is also presented.
Document ID
19840021020
Acquisition Source
Legacy CDMS
Document Type
Contractor Report (CR)
Authors
Wade, T. E.
(Mississippi State Univ. Mississippi State, MS, United States)
Date Acquired
September 4, 2013
Publication Date
March 1, 1982
Subject Category
Electronics And Electrical Engineering
Report/Patent Number
NASA-CR-162039
MSSU-EIRS-EE-82-2-PT-2
NAS 1.26:162039
Report Number: NASA-CR-162039
Report Number: MSSU-EIRS-EE-82-2-PT-2
Report Number: NAS 1.26:162039
Accession Number
84N29089
Funding Number(s)
CONTRACT_GRANT: NAS8-33448
Distribution Limits
Public
Copyright
Work of the US Gov. Public Use Permitted.
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