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Optimal expression evaluation for data parallel architecturesA data parallel machine represents an array or other composite data structure by allocating one processor (at least conceptually) per data item. A pointwise operation can be performed between two such arrays in unit time, provided their corresponding elements are allocated in the same processors. If the arrays are not aligned in this fashion, the cost of moving one or both of them is part of the cost of the operation. The choice of where to perform the operation then affects this cost. If an expression with several operands is to be evaluated, there may be many choices of where to perform the intermediate operations. An efficient algorithm is given to find the minimum-cost way to evaluate an expression, for several different data parallel architectures. This algorithm applies to any architecture in which the metric describing the cost of moving an array is robust. This encompasses most of the common data parallel communication architectures, including meshes of arbitrary dimension and hypercubes. Remarks are made on several variations of the problem, some of which are solved and some of which remain open.
Document ID
19920002478
Acquisition Source
Legacy CDMS
Document Type
Contractor Report (CR)
Authors
Gilbert, John R.
(Xerox Palo Alto Research Center CA., United States)
Schreiber, Robert
(Research Inst. for Advanced Computer Science Moffett Field, CA, United States)
Date Acquired
September 6, 2013
Publication Date
April 24, 1990
Subject Category
Computer Systems
Report/Patent Number
RIACS-TR-90-15
NASA-CR-187773
NAS 1.26:187773
Report Number: RIACS-TR-90-15
Report Number: NASA-CR-187773
Report Number: NAS 1.26:187773
Accession Number
92N11696
Funding Number(s)
CONTRACT_GRANT: NCC2-387
Distribution Limits
Public
Copyright
Work of the US Gov. Public Use Permitted.
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