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Splash 2Splash 2 is an attached processor system for Sun SPARC 2 workstations that uses Xilinx 4010 Field Programmable Gate Arrays (FPGA's) as its processing elements. The purpose of this paper is to describe Splash 2. The predecessor system, Splash 1, was designed to be used as a systolic processing system. Although it was very successful in that mode, there were many other applications that were not systolic, but which were successful, nonetheless, on Splash 1, or that were not implemented successfully due to one or more architectural limitations, most notably I/O bandwidth and interprocessor communication. Although other uses to increase computational performance have been found for the Xilinx FPGA's that are Splash's processing elements. Splash is unique in its goal to be programmable in a general sense.
Document ID
19930016386
Acquisition Source
Legacy CDMS
Document Type
Conference Paper
Authors
Arnold, Jeffrey M.
(Supercomputer Research Center Bowie, MD, United States)
Buell, Duncan A.
(Supercomputer Research Center Bowie, MD, United States)
Kleinfelder, Walter J.
(Supercomputer Research Center Bowie, MD, United States)
Date Acquired
September 6, 2013
Publication Date
February 1, 1993
Publication Information
Publication: NASA, Washington, Technology 2002: The Third National Technology Transfer Conference and Exposition, Volume 1
Subject Category
Computer Programming And Software
Accession Number
93N25575
Distribution Limits
Public
Copyright
Work of the US Gov. Public Use Permitted.
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