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Technology, design, simulation, and evaluation for SEP-hardened circuitsThis paper describes the technology, design, simulation, and evaluation for improvement of the Single Event Phenomena (SEP) hardness of gate-array and SRAM cells. Through the use of design and processing techniques, it is possible to achieve an SEP error rate less than 1.0 x 10(exp -10) errors/bit-day for a 9O percent worst-case geosynchronous orbit environment.
Document ID
19940013879
Acquisition Source
Legacy CDMS
Document Type
Conference Paper
Authors
Adams, J. R. (United Technologies Corp. Colorado Springs, CO, United States)
Allred, D. (United Technologies Corp. Colorado Springs, CO, United States)
Barry, M. (United Technologies Corp. Colorado Springs, CO, United States)
Rudeck, P. (United Technologies Corp. Colorado Springs, CO, United States)
Woodruff, R. (United Technologies Corp. Colorado Springs, CO, United States)
Hoekstra, J. (United Technologies Corp. Colorado Springs, CO, United States)
Gardner, H. (United Technologies Corp. Colorado Springs, CO, United States)
Date Acquired
September 6, 2013
Publication Date
January 1, 1991
Publication Information
Publication: Idaho Univ., The 1991 3rd NASA Symposium on VLSI Design
Subject Category
Electronics And Electrical Engineering
Accession Number
94N18352
Distribution Limits
Public
Copyright
Work of the US Gov. Public Use Permitted.

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