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Formal hardware verification of digital circuitsThe use of formal methods to verify the correctness of digital circuits is less constrained by the growing complexity of digital circuits than conventional methods based on exhaustive simulation. This paper briefly outlines three main approaches to formal hardware verification: symbolic simulation, state machine analysis, and theorem-proving.
Document ID
19940013894
Acquisition Source
Legacy CDMS
Document Type
Conference Paper
Authors
Joyce, J.
(British Columbia Univ. Vancouver British Columbia, Canada)
Seger, C.-J.
(British Columbia Univ. Vancouver British Columbia, Canada)
Date Acquired
September 6, 2013
Publication Date
January 1, 1991
Publication Information
Publication: Idaho Univ., The 1991 3rd NASA Symposium on VLSI Design
Subject Category
Electronics And Electrical Engineering
Accession Number
94N18367
Distribution Limits
Public
Copyright
Work of the US Gov. Public Use Permitted.
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