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design of cmos logic gates for tid radiationThe rise time, fall time and propagation delay of the logic gates were derived. The effects of total ionizing dose (TID) radiation on the fall and rise times of CMOS logic gates were obtained using C program calculations and PSPICE simulations. The variations of mobility and threshold voltage on MOSFET transistors when subjected to TID radiation were used to determine the dependence of switching times on TID. The results of this work indicate that by increasing the size of P-channel transistor with respect to the N-channel transistors of the CMOS gates, the propagation delay of CMOS logic gate can be made to decrease with, or be independent of an increase in TID radiation.
Document ID
19940016610
Document Type
Conference Paper
Authors
Attia, John Okyere
(Prairie View Agricultural and Mechanical Coll. TX, United States)
Sasabo, Maria L.
(Prairie View Agricultural and Mechanical Coll. TX, United States)
Date Acquired
September 6, 2013
Publication Date
January 1, 1993
Publication Information
Publication: New Mexico Univ., The Fifth NASA Symposium on VLSI Design
Subject Category
ELECTRONICS AND ELECTRICAL ENGINEERING
Funding Number(s)
CONTRACT_GRANT: NAG9-337
Distribution Limits
Public
Copyright
Work of the US Gov. Public Use Permitted.

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