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test results for seu and sel immune memory circuitsTest results for three SEU logic/circuit hardened CMOS memory circuits verify upset and latch-up immunity for two configurations to be in excess of 120 MeV cm(exp 2)/mg using a commercial, non-radiation hardened CMOS process. Test chips from three separate fabrication runs in two different process were evaluated.
Document ID
19940016614
Document Type
Conference Paper
Authors
Wiseman, D.
(New Mexico Univ. Albuquerque, NM, United States)
Canaris, J.
(New Mexico Univ. Albuquerque, NM, United States)
Whitaker, S.
(New Mexico Univ. Albuquerque, NM, United States)
Gambles, J.
(New Mexico Univ. Albuquerque, NM, United States)
Arave, K.
(New Mexico Univ. Albuquerque, NM, United States)
Arave, L.
(New Mexico Univ. Albuquerque, NM, United States)
Date Acquired
September 6, 2013
Publication Date
January 1, 1993
Publication Information
Publication: The Fifth NASA Symposium on VLSI Design
Subject Category
ELECTRONICS AND ELECTRICAL ENGINEERING
Distribution Limits
Public
Copyright
Work of the US Gov. Public Use Permitted.

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