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an asic memory buffer controller for a high speed disk systemThe need for large capacity, high speed mass memory storage devices has become increasingly evident at NASA during the past decade. High performance mass storage systems are crucial to present and future NASA systems. Spaceborne data storage system requirements have grown in response to the increasing amounts of data generated and processed by orbiting scientific experiments. Predictions indicate increases in the volume of data by orders of magnitude during the next decade. Current predictions are for storage capacities on the order of terabits (Tb), with data rates exceeding one gigabit per second (Gbps). As part of the design effort for a state of the art mass storage system, NASA Langley has designed a 144 CMOS ASIC to support high speed data transfers. This paper discusses the system architecture, ASIC design and some of the lessons learned in the development process.
Document ID
19940016616
Document Type
Conference Paper
Authors
Hodson, Robert F.
(Christopher Newport Coll. Newport News, VA, United States)
Campbell, Steve
(Christopher Newport Coll. Newport News, VA, United States)
Date Acquired
September 6, 2013
Publication Date
January 1, 1993
Publication Information
Publication: New Mexico Univ., The Fifth NASA Symposium on VLSI Design
Subject Category
COMPUTER OPERATIONS AND HARDWARE
Distribution Limits
Public
Copyright
Work of the US Gov. Public Use Permitted.

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