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digital receiver for on-board fm/fsk-fm/bpsk demodulationAn all-digital demodulator FM/FSK-FM/BPSK is presented. The proposed architecture allows the 1-bit IF down-sampling technique with the hardware simplification of receiver analog section. The receiver exhibits great flexibility both in terms of signal demodulation (FSK or BPSK, subcarrier/ tone frequency, data rate) and interface capability. The demodulator is going to be realized in a VLSI chip (20 Kgate complexity). This paper describes the demodulator structure and its demodulation performances obtained with a breadboard based on programmable logic devices. The choice of a simple and effective scheme for frequency detection (FM and FSK demodulators) is suggested by system design considerations as well. Signal processing algorithms include also a Costas carrier phase recovery scheme in the case of BPSK signal and data transition tracking loop for the bit clock recovery. Test results address this solution as one of the most suitable for TT&C space application.
Document ID
19940016618
Document Type
Conference Paper
Authors
Boscagli, G.
(Alenia Spazio S.p.A. Rome, Italy)
Comparini, M. C.
(Alenia Spazio S.p.A. Rome, Italy)
Martone, M.
(Alenia Spazio S.p.A. Rome, Italy)
Date Acquired
September 6, 2013
Publication Date
January 1, 1993
Publication Information
Publication: New Mexico Univ., The Fifth NASA Symposium on VLSI Design
Subject Category
COMMUNICATIONS AND RADAR
Distribution Limits
Public
Copyright
Work of the US Gov. Public Use Permitted.

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