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correct cmos ic defect models for quality testingLeading edge, high reliability, and low escape CMOS IC test practices have now virtually removed the stuck-at fault model and replaced it with more defect-orientated models. Quiescent power supply current testing (I(sub DDQ)) combined with strategic use of high speed test patterns is the recommended approach to zero defect and high reliability testing goals. This paper reviews the reasons for the change in CMOS IC test practices and outlines an improved CMOS IC test methodology.
Document ID
19940016620
Document Type
Conference Paper
Authors
Soden, Jerry M.
(Sandia National Labs. Albuquerque, NM, United States)
Hawkins, Charles F.
(New Mexico Univ. Albuquerque., United States)
Date Acquired
September 6, 2013
Publication Date
January 1, 1993
Publication Information
Publication: New Mexico Univ., The Fifth NASA Symposium on VLSI Design
Subject Category
QUALITY ASSURANCE AND RELIABILITY
Funding Number(s)
CONTRACT_GRANT: DE-AC04-76DP-00789
Distribution Limits
Public
Copyright
Work of the US Gov. Public Use Permitted.

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