NTRS - NASA Technical Reports Server

Back to Results
power optimization in logic isomersLogic isomers are labeled, 2-isomorphic graphs that implement the same logic function. Logic isomers may have significantly different power requirements even though they have the same number of transistors in the implementation. The power requirements of the isomers depend on the transition activity of the input signals. The power requirements of isomorphic graph isomers of n-input NAND and NOR gates are shown. Choosing the less power-consuming isomer instead of the others can yield significant power savings. Experimental results on a ripple-carry adder are presented to show that the implementation using the least power-consuming isomers requires approximately 10 percent less power than the implementation using the most power-consuming isomers. Simulations of other random logic designs also confirm that designs using less power-consuming isomers can reduce the logic power demand by approximately 10 percent as compared to designs using more power-consuming isomers.
Document ID
Document Type
Conference Paper
Panwar, Ramesh
(California Univ. Los Angeles., United States)
Rennels, David
(California Univ. Los Angeles., United States)
Alkalaj, Leon
(Jet Propulsion Lab., California Inst. of Tech. Pasadena, CA, United States)
Date Acquired
September 6, 2013
Publication Date
January 1, 1993
Publication Information
Publication: New Mexico Univ., The Fifth NASA Symposium on VLSI Design
Subject Category
Funding Number(s)
CONTRACT_GRANT: N00014-91-J-1009
Distribution Limits
Work of the US Gov. Public Use Permitted.

Related Records

IDRelationTitle19940016163Analytic PrimaryTwenty-Fourth Lunar and Planetary Science Conference. Part 3: N-Z