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Mixed voltage VLSI designA technique for minimizing the power dissipated in a Very Large Scale Integration (VLSI) chip by lowering the operating voltage without any significant penalty in the chip throughput even though low voltage operation results in slower circuits. Since the overall throughput of a VLSI chip depends on the speed of the critical path(s) in the chip, it may be possible to sustain the throughput rates attained at higher voltages by operating the circuits in the critical path(s) with a high voltage while operating the other circuits with a lower voltage to minimize the power dissipation. The interface between the gates which operate at different voltages is crucial for low power dissipation since the interface may possibly have high static current dissipation thus negating the gains of the low voltage operation. The design of a voltage level translator which does the interface between the low voltage and high voltage circuits without any significant static dissipation is presented. Then, the results of the mixed voltage design using a greedy algorithm on three chips for various operating voltages are presented.
Document ID
Document Type
Conference Paper
Panwar, Ramesh
(California Univ. Los Angeles., United States)
Rennels, David
(California Univ. Los Angeles., United States)
Alkalaj, Leon
(Jet Propulsion Lab., California Inst. of Tech. Pasadena, CA, United States)
Date Acquired
September 6, 2013
Publication Date
January 1, 1993
Publication Information
Publication: New Mexico Univ., The Fifth NASA Symposium on VLSI Design
Subject Category
Electronics And Electrical Engineering
Accession Number
Funding Number(s)
CONTRACT_GRANT: N00014-91-J-1009
Distribution Limits
Work of the US Gov. Public Use Permitted.
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