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test pattern generation for ila sequential circuitsAn efficient method of generating test patterns for sequential machines implemented using one-dimensional, unilateral, iterative logic arrays (ILA's) of BTS pass transistor networks is presented. Based on a transistor level fault model, the method affords a unique opportunity for real-time fault detection with improved fault coverage. The resulting test sets are shown to be equivalent to those obtained using conventional gate level models, thus eliminating the need for additional test patterns. The proposed method advances the simplicity and ease of the test pattern generation for a special class of sequential circuitry.
Document ID
19940016634
Document Type
Conference Paper
Authors
Feng, YU
(Allied-Signal Corp. Olathe, KS, United States)
Frenzel, James F.
(Idaho Univ. Moscow., United States)
Maki, Gary K.
(New Mexico Univ. Albuquerque., United States)
Date Acquired
September 6, 2013
Publication Date
January 1, 1993
Publication Information
Publication: New Mexico Univ., The Fifth NASA Symposium on VLSI Design
Subject Category
ELECTRONICS AND ELECTRICAL ENGINEERING
Funding Number(s)
CONTRACT_GRANT: NAGW-3293
Distribution Limits
Public
Copyright
Work of the US Gov. Public Use Permitted.

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