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testing self-timed circuits using scan pathsTesting is an essential part of any digital system design and one that can be made much easier if testing is considered during the design process rather than after the system is complete. There are a number of techniques for integrating testability into system design, but many of these traditional testing methods used for synchronous circuits are not directly applicable to non-clocked asynchronous circuits. As a result, many asynchronous circuits do not employ design for testability techniques. A method of using the familiar model of scan paths modified to test self-timed systems are presented. Specifically, circuits designed using a library of self-timed modules to assemble systems with two-phase transition control and bundled data paths are considered. The method involves modifying these self-timed modules such that circuits designed from them have a built-in scan path.
Document ID
19940016636
Document Type
Conference Paper
Authors
Khoche, Ajay
(Utah Univ. Salt Lake City, UT, United States)
Brunvand, Erik L.
(Utah Univ. Salt Lake City, UT, United States)
Date Acquired
September 6, 2013
Publication Date
January 1, 1993
Publication Information
Publication: New Mexico Univ., The Fifth NASA Symposium on VLSI Design
Subject Category
ELECTRONICS AND ELECTRICAL ENGINEERING
Distribution Limits
Public
Copyright
Work of the US Gov. Public Use Permitted.

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