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experiments on technology mapping using different cell librariesTechnology mapping is one of the major steps in the synthesis process of integrated circuits. Efficient algorithms have been proposed in the recent past to optimize the number of cells required to implement a given design, but not enough effort has been spent in studying the relationship between the quality of the circuit produced by the logic synthesis tool and the cell library used to perform the mapping. In this paper we present experiments on technology mapping that show how the design of the cell library can influence the area and the delay of the synthesized circuit.
Document ID
19940016645
Document Type
Conference Paper
Authors
Macii, Enrico
(Politecnico di Torino Italy)
Poncino, Massimo
(Politecnico di Torino Italy)
Date Acquired
September 6, 2013
Publication Date
January 1, 1993
Publication Information
Publication: New Mexico Univ., The Fifth NASA Symposium on VLSI Design
Subject Category
ELECTRONICS AND ELECTRICAL ENGINEERING
Distribution Limits
Public
Copyright
Work of the US Gov. Public Use Permitted.

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