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reliable interface design for combining asynchronous and synchronous circuitsIn order to successfully integrate asynchronous and synchronous designs, great care must be taken at the interface between the two types of systems. Synchronizing asynchronous inputs with a free running clock can cause well-known problems with metastability in the synchronization circuits. Stretchable clocks allow a clock cycle to expand dynamically in response to the metastability effects of sampling asynchronous inputs. We use an interface organization where the special circuitry for detecting metastability and for stretching the clock that is delivered to the synchronous part of the system is encapsulated in a Q-flop-based interface. This provides a very convenient method for interfacing mixed systems, as the interface and clock generation circuitry are isolated into one special module, and neither the asynchronous nor the synchronous system need be modified internally to accommodate the interface. This is especially important when standard synchronous components are used as there is no opportunity to modify these parts. We show that this interface module is suitable for most mixed design needs and conclude with an example.
Document ID
Document Type
Conference Paper
Josephson, Lueli
(Utah Univ. Salt Lake City, UT, United States)
Brunvand, Erik L.
(Utah Univ. Salt Lake City, UT, United States)
Gopalakrishan, Ganesh
(Utah Univ. Salt Lake City, UT, United States)
Hurdle, John F.
(Utah Univ. Salt Lake City, UT, United States)
Date Acquired
September 6, 2013
Publication Date
January 1, 1993
Publication Information
Publication: New Mexico Univ., The Fifth NASA Symposium on VLSI Design
Subject Category
Distribution Limits
Work of the US Gov. Public Use Permitted.

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