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design methods for fault-tolerant finite state machinesVLSI electronic circuits are increasingly being used in space-borne applications where high levels of radiation may induce faults, known as single event upsets. In this paper we review the classical methods of designing fault tolerant digital systems, with an emphasis on those methods which are particularly suitable for VLSI-implementation of finite state machines. Four methods are presented and will be compared in terms of design complexity, circuit size, and estimated circuit delay.
Document ID
19940016647
Document Type
Conference Paper
Authors
Niranjan, Shailesh
(Idaho Univ. Moscow, ID, United States)
Frenzel, James F.
(Idaho Univ. Moscow, ID, United States)
Date Acquired
September 6, 2013
Publication Date
January 1, 1993
Publication Information
Publication: New Mexico Univ., The Fifth NASA Symposium on VLSI Design
Subject Category
ELECTRONICS AND ELECTRICAL ENGINEERING
Distribution Limits
Public
Copyright
Work of the US Gov. Public Use Permitted.

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