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automated synthesis and verification of configurable dram blocks for asic'sA highly flexible embedded DRAM compiler is developed which can generate DRAM blocks in the range of 256 bits to 256 Kbits. The compiler is capable of automatically verifying the functionality of the generated DRAM modules. The fully automated verification capability is a key feature that ensures the reliability of the generated blocks. The compiler's architecture, algorithms, verification techniques and the implementation methodology are presented.
Document ID
19940016650
Document Type
Conference Paper
Authors
Pakkurti, M.
(Toledo Univ. OH, United States)
Eldin, A. G.
(Toledo Univ. OH, United States)
Kwatra, S. C.
(Toledo Univ. OH, United States)
Jamali, M.
(Toledo Univ. OH, United States)
Date Acquired
September 6, 2013
Publication Date
January 1, 1993
Publication Information
Publication: New Mexico Univ., The Fifth NASA Symposium on VLSI Design
Subject Category
ELECTRONICS AND ELECTRICAL ENGINEERING
Funding Number(s)
CONTRACT_GRANT: NAG3-799
Distribution Limits
Public
Copyright
Work of the US Gov. Public Use Permitted.

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