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A cost-effective methodology for the design of massively-parallel VLSI functional unitsIn this paper we propose a generalized methodology for the design of cost-effective massively-parallel VLSI Functional Units. This methodology is based on a technique of generating and reducing a massive bit-array on the mask-programmable PAcube VLSI array. This methodology unifies (maintains identical data flow and control) the execution of complex arithmetic functions on PAcube arrays. It is highly regular, expandable and uniform with respect to problem-size and wordlength, thereby reducing the communication complexity. The memory-functional unit interface is regular and expandable. Using this technique functional units of dedicated processors can be mask-programmed on the naked PAcube arrays, reducing the turn-around time. The production cost of such dedicated processors can be drastically reduced since the naked PAcube arrays can be mass-produced. Analysis of the the performance of functional units designed by our method yields promising results.
Document ID
Document Type
Conference Paper
Venkateswaran, N.
(Sri Venkateswara Univ. Tirupati, India)
Sriram, G.
(Sri Venkateswara Univ. Tirupati, India)
Desouza, J.
(Sri Venkateswara Univ. Tirupati, India)
Date Acquired
September 6, 2013
Publication Date
January 1, 1993
Publication Information
Publication: New Mexico Univ., The Fifth NASA Symposium on VLSI Design
Subject Category
Computer Systems
Accession Number
Distribution Limits
Work of the US Gov. Public Use Permitted.

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