NASA Logo

NTRS

NTRS - NASA Technical Reports Server

Collections About News Help Login

Press Enter or click the Search button to begin your search.

Back to Results
Integrated Circuit ImmunityThis paper presents a DOD E3 program overview on integrated circuit immunity. The topics include: 1) EMI Immunity Testing; 2) Threshold Definition; 3) Bias Tee Function; 4) Bias Tee Calibration Set-Up; 5) EDM Test Figure; 6) EMI Immunity Levels; 7) NAND vs. and Gate Immunity; 8) TTL vs. LS Immunity Levels; 9) TP vs. OC Immunity Levels; 10) 7805 Volt Reg Immunity; and 11) Seventies Chip Set. This paper is presented in viewgraph form.
Document ID
20000072486
Acquisition Source
Marshall Space Flight Center
Document Type
Preprint (Draft being sent to journal)
Authors
Sketoe, J. G. (Boeing Co. Saint Louis, MO United States)
Clark, Anthony (NASA Marshall Space Flight Center Huntsville, AL United States)
Date Acquired
September 7, 2013
Publication Date
January 1, 2000
Subject Category
Communications And Radar
Meeting Information
Meeting: Electromagnetic Environmental Effects Review Meeting
Location: Orlando, FL
Country: United States
Start Date: April 11, 2000
End Date: April 14, 2000
Sponsors: Department of Defense
Funding Number(s)
CONTRACT_GRANT: NAS8-98217
Distribution Limits
Public
Copyright
Work of the US Gov. Public Use Permitted.

Related Records

There are no records associated with this record.
No Preview Available