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STRS Compliant FPGA Waveform DevelopmentThe Space Telecommunications Radio System (STRS) Architecture Standard describes a standard for NASA space software defined radios (SDRs). It provides a common framework that can be used to develop and operate a space SDR in a reconfigurable and reprogrammable manner. One goal of the STRS Architecture is to promote waveform reuse among multiple software defined radios. Many space domain waveforms are designed to run in the special signal processing (SSP) hardware. However, the STRS Architecture is currently incomplete in defining a standard for designing waveforms in the SSP hardware. Therefore, the STRS Architecture needs to be extended to encompass waveform development in the SSP hardware. The extension of STRS to the SSP hardware will promote easier waveform reconfiguration and reuse. A transmit waveform for space applications was developed to determine ways to extend the STRS Architecture to a field programmable gate array (FPGA). These extensions include a standard hardware abstraction layer for FPGAs and a standard interface between waveform functions running inside a FPGA. A FPGA-based transmit waveform implementation of the proposed standard interfaces on a laboratory breadboard SDR will be discussed.
Document ID
Document Type
Conference Paper
Nappier, Jennifer
(NASA Glenn Research Center Cleveland, OH, United States)
Downey, Joseph
(NASA Glenn Research Center Cleveland, OH, United States)
Mortensen, Dale
(ASRC Aerospace Corp. Cleveland, OH, United States)
Date Acquired
August 24, 2013
Publication Date
October 1, 2008
Subject Category
Space Communications, Spacecraft Communications, Command And Tracking
Report/Patent Number
Meeting Information
Software Defined Radio (SDR) Technical Conference(Washington, D.C.)
Distribution Limits
Public Use Permitted.
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