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STRS Compliant FPGA Waveform DevelopmentThe Space Telecommunications Radio System (STRS) Architecture Standard describes a standard for NASA space software defined radios (SDRs). It provides a common framework that can be used to develop and operate a space SDR in a reconfigurable and reprogrammable manner. One goal of the STRS Architecture is to promote waveform reuse among multiple software defined radios. Many space domain waveforms are designed to run in the special signal processing (SSP) hardware. However, the STRS Architecture is currently incomplete in defining a standard for designing waveforms in the SSP hardware. Therefore, the STRS Architecture needs to be extended to encompass waveform development in the SSP hardware. A transmit waveform for space applications was developed to determine ways to extend the STRS Architecture to a field programmable gate array (FPGA). These extensions include a standard hardware abstraction layer for FPGAs and a standard interface between waveform functions running inside a FPGA. Current standards were researched and new standard interfaces were proposed. The implementation of the proposed standard interfaces on a laboratory breadboard SDR will be presented.
Document ID
Document Type
Nappier, Jennifer
(NASA Glenn Research Center Cleveland, OH, United States)
Downey, Joseph
(NASA Glenn Research Center Cleveland, OH, United States)
Date Acquired
August 27, 2013
Publication Date
October 30, 2008
Subject Category
Communications And Radar
Report/Patent Number
Meeting Information
Software Defined Radio (SDR) Technical Conference(Washington, DC)
Funding Number(s)
WBS: WBS 439432.04.07.01
Distribution Limits
Work of the US Gov. Public Use Permitted.
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