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G4-FETs as Universal and Programmable Logic GatesAn analysis of a patented generic silicon- on-insulator (SOI) electronic device called a G4-FET has revealed that the device could be designed to function as a universal and programmable logic gate. The universality and programmability could be exploited to design logic circuits containing fewer discrete components than are required for conventional transistor-based circuits performing the same logic functions. A G4-FET is a combination of a junction field-effect transistor (JFET) and a metal oxide/semiconductor field-effect transistor (MOSFET) superimposed in a single silicon island and can therefore be regarded as two transistors sharing the same body. A G4-FET can also be regarded as a single transistor having four gates: two side junction-based gates, a top MOS gate, and a back gate activated by biasing of the SOI substrate. Each of these gates can be used to control the conduction characteristics of the transistor; this possibility creates new options for designing analog, radio-frequency, mixed-signal, and digital circuitry. With proper choice of the specific dimensions for the gates, channels, and ancillary features of the generic G4-FET, the device could be made to function as a three-input, one-output logic gate. As illustrated by the truth table in the top part of the figure, the behavior of this logic gate would be the inverse (the NOT) of that of a majority gate. In other words, the device would function as a NOT-majority gate. By simply adding an inverter, one could obtain a majority gate. In contrast, to construct a majority gate in conventional complementary metal oxide/semiconductor (CMOS) circuitry, one would need four three-input AND gates and a four-input OR gate, altogether containing 32 transistors.
Document ID
20100002820
Acquisition Source
Jet Propulsion Laboratory
Document Type
Other - NASA Tech Brief
Authors
Johnson, Travis
(California Inst. of Tech. Pasadena, CA, United States)
Fijany, Amir
(California Inst. of Tech. Pasadena, CA, United States)
Mojarradi, Mohammad
(California Inst. of Tech. Pasadena, CA, United States)
Vatan, Farrokh
(California Inst. of Tech. Pasadena, CA, United States)
Toomarian, Nikzad
(California Inst. of Tech. Pasadena, CA, United States)
Kolawa, Elizabeth
(California Inst. of Tech. Pasadena, CA, United States)
Cristoloveanu, Sorin
(California Inst. of Tech. Pasadena, CA, United States)
Blalock, Benjamin
(California Inst. of Tech. Pasadena, CA, United States)
Date Acquired
August 25, 2013
Publication Date
July 1, 2007
Publication Information
Publication: NASA Tech Briefs, July 2007
Subject Category
Man/System Technology And Life Support
Report/Patent Number
NPO-41698
Distribution Limits
Public
Copyright
Public Use Permitted.
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