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Single Event Effects in FPGA Devices 2014-2015This presentation provides an overview of single event effects in FPGA devices 2014-2015 including commercial Xilinx V5 heavy ion accelerated testing, Xilinx Kintex-7 heavy ion accelerated testing. Mitigation study, and investigation of various types of triple modular redundancy (TMR) for commercial SRAM based FPGAs.
Document ID
20150015964
Acquisition Source
Goddard Space Flight Center
Document Type
Presentation
Authors
Berg, Melanie D. (ASRC Federal Space and Defense Greenbelt, MD, United States)
LaBel, Kenneth A. (NASA Goddard Space Flight Center Greenbelt, MD United States)
Pellish, Jonathan (NASA Goddard Space Flight Center Greenbelt, MD United States)
Date Acquired
August 13, 2015
Publication Date
June 23, 2015
Subject Category
Electronics And Electrical Engineering
Report/Patent Number
GSFC-E-DAA-TN24313
Report Number: GSFC-E-DAA-TN24313
Meeting Information
Meeting: NASA Electronic Parts and Packaging Program, Electronics Technology Workshop (NEPP-ETW)
Location: Greenbelt, MD
Country: United States
Start Date: June 23, 2015
End Date: June 26, 2015
Sponsors: NASA Goddard Space Flight Center
Funding Number(s)
CONTRACT_GRANT: NNG13CR48C
Distribution Limits
Public
Copyright
Public Use Permitted.
Keywords
Single event upset (SEU)
Xilinx V5
Single Event Upset (SEU) Testing
Xilinx Kintex-7
Single event latch-up (SEL)
Field Programmable Gate Array (FPGA)
Virtex-5QV

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