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One Time Programmable Antifuse Memory Based on Bulk Junctionless TransistorOne time programmable (OTP) antifuse base memory is demonstrated based on a bulk junctionless gate-all-around (GAA) nanowire transistor technology. The presented memory consists of a single transistor (1T) footprint without any process modification. The source/drain (S/D) and gate respectively become bit line and word line where the antifuse is formed by oxide breakdown across the gate and the channel. The channel is connected directly to the bit line due to junctionless S/D and inherently isolated from the neighboring cell by the GAA channel. Therefore, an array of 1T antifuse OTP can be a candidate for the sub-5-nanometer technology node.
Document ID
20190002597
Acquisition Source
Ames Research Center
Document Type
Preprint (Draft being sent to journal)
Authors
Jin-Woo Han ORCID
(Universities Space Research Association Columbia, Maryland, United States)
Dong-Il Moon ORCID
(Universities Space Research Association Columbia, Maryland, United States)
M Meyyappan
(Ames Research Center Mountain View, California, United States)
Date Acquired
April 18, 2019
Publication Date
June 19, 2018
Publication Information
Publication: IEEE Electron Device Letters
Publisher: Institute of Electrical and Electronics Engineers
Volume: 39
Issue: 8
Issue Publication Date: August 1, 2018
ISSN: 0741-3106
e-ISSN: 1558-0563
Subject Category
Electronics And Electrical Engineering
Report/Patent Number
ARC-E-DAA-TN56598
Funding Number(s)
CONTRACT_GRANT: NNA16BD14C
Distribution Limits
Public
Copyright
Public Use Permitted.
Technical Review
Single Expert
Keywords
Antifuse
OTP memory
Embedded non-volatile memory (NVM)
Junctionless transistor
Logic compatible NVM
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