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Technical Primer on Design and SPICE Modeling of Circuits for NASA Glenn SiC JFET IC Version 12 Prototype Wafer Run Part 1: SiC JFET Behavior and SPICE ModelingThis presentation illustratively communicates how to SPICE model silicon carbide (SiC) SiC junction field effect transistors (JFETs) for designing circuits for NASA GRC's upcoming prototype fabrication of SiC JFET IC Version 12.
Document ID
20190026451
Acquisition Source
Glenn Research Center
Document Type
Presentation
Authors
Neudeck, Philip G.
(NASA Glenn Research Center Cleveland, OH, United States)
Date Acquired
June 18, 2019
Publication Date
May 1, 2019
Subject Category
Electronics And Electrical Engineering
Report/Patent Number
GRC-E-DAA-TN68630
Funding Number(s)
WBS: 161682.04.03.01.18
Distribution Limits
Public
Copyright
Work of the US Gov. Public Use Permitted.
Keywords
silicon carbide
JFET
integrated circuits
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