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Technical Primer on Design and SPICE Modeling of Circuits for NASA Glenn SiC JFET IC Generation 13 Prototype Wafer Run - Part 1: SiC JFET Behavior and SPICE ModelingGoal: Enable anyone to SPICE-model and design 500 °C durable integrated circuits for their intended application.
Document ID
20210015705
Acquisition Source
Glenn Research Center
Document Type
Other - Graphical technical primer file in view graph presentation format
Authors
Philip G Neudeck (Glenn Research Center Cleveland, Ohio, United States)
Date Acquired
May 17, 2021
Publication Date
May 26, 2021
Publication Information
Publication: Public website
Publisher: NASA Glenn Research Center
URL: https://go.nasa.gov/jfetic
Subject Category
Electronics And Electrical Engineering
Funding Number(s)
WBS: 427922.04.02.01
Distribution Limits
Public
Copyright
Work of the US Gov. Public Use Permitted.
Technical Review
NASA Technical Management
Keywords
silicon carbide
JFET
integrated circuit
circuit design
circuit modeling

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