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Single Event Effects in FPGA Devices 2015-2016This presentation provides an overview of single event effects in FPGA devices 2015-2016 including commercial Xilinx V5 heavy ion accelerated testing, Xilinx Kintex-7 heavy ion accelerated testing, mitigation study, and investigation of various types of triple modular redundancy (TMR) for commercial SRAM based FPGAs.
Document ID
20160007754
Document Type
Presentation
Authors
Berg, Melanie (ASRC Federal Space and Defense Greenbelt, MD, United States)
LaBel, Kenneth (NASA Goddard Space Flight Center Greenbelt, MD United States)
Pellish, Jonathan (NASA Goddard Space Flight Center Greenbelt, MD United States)
Date Acquired
June 20, 2016
Publication Date
June 13, 2016
Subject Category
Electronics and Electrical Engineering
Report/Patent Number
GSFC-E-DAA-TN32953
Meeting Information
2016 NEPP Electronics Technology Workshop (ETW)(Greenbelt, MD)
Funding Number(s)
CONTRACT_GRANT: NNG13CR48C
Distribution Limits
Public
Copyright
Public Use Permitted.
Keywords
Xilinx V5
Single event latch-up (SEL)
Field Programmable Gate Array (FPGA)
Single Event Upset (SEU) Testing
Virtex-5QV
Xilinx Kintex-7
Single event upset (SEU)

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