FPGA Mitigation Strategies for Critical Applications

Technology is changing at a fast pace. Transistor geometries are getting smaller, voltage thresholds are getting lower, design complexity is exponentially increasing, and user options are expanding. Consequently, reliable insertion of error detection and correction (EDAC) circuitry has become relatively challenging. As a response, a variety of mitigation techniques are being evaluated. They range from weak EDAC circuits that save area and power to strong mitigation strategies that are a great expense to systems. This presentation will focus on radiation induced susceptibilities for a variety of FPGA types and ASIC devices. In addition, the user will be provided information on applicable mitigation strategies per device.