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Cellular logic array for computation of squaresA cellular logic array is described for squaring binary numbers. This array offers a significant increase in speed, with a relatively small hardware overhead. This improvement is a result of novel implementation of the formula (x + y)exp 2 = x(exp 2) + y(exp 2) + 2(x)(y). These results can also be incorporated in the existing arrays achieving considerable hardware reduction.
Document ID
19940013870
Acquisition Source
Legacy CDMS
Document Type
Conference Paper
Authors
Shamanna, M.
(Idaho Univ. Moscow, ID, United States)
Whitaker, S.
(Idaho Univ. Moscow, ID, United States)
Canaris, J.
(Idaho Univ. Moscow, ID, United States)
Date Acquired
September 6, 2013
Publication Date
January 1, 1991
Publication Information
Publication: The 1991 3rd NASA Symposium on VLSI Design
Subject Category
Electronics And Electrical Engineering
Accession Number
94N18343
Funding Number(s)
CONTRACT_GRANT: NAGW-1406
Distribution Limits
Public
Copyright
Work of the US Gov. Public Use Permitted.
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