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Practical SiC JFET-R Analog Integrated Circuit Design for Extreme Environment ApplicationsSilicon carbide (SiC) junction field effect transistor and SiC resistor (SiC JFET-R) integrated circuits(ICs) have uniquely demonstrated prolonged operation above 450 °C that promises significant operational improvements to a variety of NASA missions. However, the SiC epiwafers used to fabricate these ICs suffer from epi-growth process immaturity that imparts large and systematic spreads in JFET threshold voltages as a function of the device distance from the center on the wafer. Furthermore, the unprecedently wide range of intended application operating temperatures (in many cases over 600 °C wide) imparts as much as 5-fold change in JFET bias currents. This Technical Memorandum documents methods by which both temperature and radius associated JFET electrical parameter variances can be adequately eliminated, or even exploited in JFET-R circuit designs. Full analog circuit examples, including operational amplifiers, and SPICE simulations across experimentally documented SiC JFET parameter extremes are given to illustrate the efficacy of these methods. The reader may use the examples in this memorandum as either an end point, to get a desired analog signal conditioning design into hardware implemented in SiC JFET-R ICs, or as a basis point from which to derive further improvement.
Document ID
Document Type
Technical Memorandum (TM)
Michael J Krasowski
(Glenn Research Center Cleveland, Ohio, United States)
Philip G Neudeck
(Glenn Research Center Cleveland, Ohio, United States)
Date Acquired
January 22, 2021
Publication Date
May 1, 2021
Subject Category
Electronics And Electrical Engineering
Report/Patent Number
Funding Number(s)
WBS: 427922.04.02.01
Distribution Limits
Work of the US Gov. Public Use Permitted.
Technical Review
NASA Peer Committee
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