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Graphical Primer of NASA Glenn SiC JFET Integrated Circuit (IC) Generation 13 LayoutHow to layout 500 °C durable integrated circuit cells for fabrication by NASA Glenn.
Document ID
20210015684
Acquisition Source
Glenn Research Center
Document Type
Other - Graphical technology guide in powerpoint format for posting on NASA public website.
Authors
Philip Neudeck (Glenn Research Center Cleveland, Ohio, United States)
David Spry (Glenn Research Center Cleveland, Ohio, United States)
Date Acquired
May 17, 2021
Publication Date
May 26, 2021
Publication Information
Publication: https://go.nasa.gov/jfetic
Publisher: NASA Glenn Research Center
Subject Category
Electronics And Electrical Engineering
Funding Number(s)
WBS: 427922.04.02.01
Distribution Limits
Public
Copyright
Work of the US Gov. Public Use Permitted.
Technical Review
NASA Technical Management
Keywords
Silicon carbide
Integrated Circuit
JFET
High Temperature

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