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Venus Surface Environmental Chamber Test of SiC JFET-R Multi-Chip Circuit BoardThis poster describes a first attempt to demonstrate a multi-chip prototype lander control and sensor signal digitization electronics circuit board comprised of ten NASA Glenn IC Generation 11 SiC JFET-R IC chips in 460 °C, 9.4 MPa harsh Venus surface conditions. The lander circuit ceased electrical operation prematurely at 107 °C as the Venus chamber heated up. Optical and SEM post-test inspections indicate fatal dielectric cracks occurred on only one of the ten SiC chips.
Document ID
20230013079
Acquisition Source
Glenn Research Center
Document Type
Poster
External Source(s)
Authors
Philip G Neudeck ORCID
(Glenn Research Center Cleveland, Ohio, United States)
Liangyu Chen
(Ohio Aerospace Institute Cleveland, Ohio, United States)
Lawrence C Greer
(Glenn Research Center Cleveland, Ohio, United States)
David J Spry
(Glenn Research Center Cleveland, Ohio, United States)
Norman F Prokop
(Glenn Research Center Cleveland, Ohio, United States)
Dorothy Lukco
(HX5 (United States) Fort Walton Beach, Florida, United States)
Michael J Krasowski
(Glenn Research Center Cleveland, Ohio, United States)
Gary W Hunter
(Glenn Research Center Cleveland, Ohio, United States)
Date Acquired
September 7, 2023
Publication Date
September 17, 2023
Subject Category
Electronics and Electrical Engineering
Meeting Information
Meeting: International Conference on Silicon Carbide and Related Materials (ICSCRM)
Location: Sorrento
Country: IT
Start Date: September 17, 2023
End Date: September 22, 2023
Sponsors: University of Naples Federico II
Funding Number(s)
WBS: 427922.04.10.01.03
CONTRACT_GRANT: NNC15BA02B
CONTRACT_GRANT: 80GRC020D0003
Distribution Limits
Public
Copyright
Public Use Permitted.
Technical Review
NASA Technical Management
Keywords
silicon carbide
JFET
Integrated Circuit
Failure Analysis
circuit board
Venus
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